The present invention relates to the initialization of a personal computer following a reset or powering on of the personal computer and, in particular, a method for transferring data from read only memory to random access memory without intervention of the central processing unit of the personal computer.
When a personal computer (xe2x80x9cPCxe2x80x9d) is powered on or reset, computer instructions comprising a number of firmware routines are transferred from a read only memory (xe2x80x9cROMxe2x80x9d) which may or may not be a programmable read only memory (xe2x80x9cPROMxe2x80x9d), to system random access memory (xe2x80x9cRAMxe2x80x9d). Following transfer of the firmware routines from the ROM to the RAM, the central processing unit (xe2x80x9cCPUxe2x80x9d) of the PC is initialized and firmware initialization routines, or bootstrap routines, are then run to initialize the remaining hardware and software components of the PC. This entire process, including the transfer of the firmware routines from the ROM to the RAM, is known as xe2x80x9cbooting a PCxe2x80x9d or as xe2x80x9cthe bootstrap process.xe2x80x9d The firmware initialization routines executed during the bootstrap process are called the xe2x80x9cbootstrap routines.xe2x80x9d
The firmware routines transferred to the RAM when a PC is booted include the routines of the basic input/output system (xe2x80x9cBIOSxe2x80x9d), an interrupt service routine, a power-on self test routine, and the various initialization routines that are executed only during the bootstrap process. These firmware routines are transferred from the ROM to the RAM under control of the CPU in a process known as read only memory (xe2x80x9cROMxe2x80x9d) shadowing. The CPU repeatedly fetches and executes the instructions for transferring the firmware routines from the ROM, as well as the instructions of the firmware routines themselves, in a multi-step process involving transfer of instructions over a relatively low-speed bus and storage of the instructions in a temporary register. Once ROM shadowing has been completed, the CPU then begins to execute the firmware routines from the system RAM.
One reason for ROM shadowing is that it is far more efficient to first perform ROM shadowing before executing the firmware routines. Fetching and executing instructions from the RAM over a relatively high-speed memory bus is so much faster than fetching and executing those same instructions over one or more relatively low-speed peripheral buses that the overhead of first transferring the firmware routines from ROM to RAM is more than offset by the faster execution of the firmware routines from RAM than from ROM.
A second reason for ROM shadowing is that, once the firmware CPU initialization routines have been executed, the firmware initialization routines can be discarded. The remaining BIOS software routines can then be more efficiently stored in the RAM and that portion of the RAM formerly occupied by the initialization routines can be used to store other data or computer instructions.
FIG. 1 is a block diagram of the basic components of currently-available PCs that are involved in ROM shadowing. The firmware routines are stored as ROM data 102 in a ROM 104. During conventional ROM shadowing, the firmware routines are transferred, under control of the CPU 106, via an ISA bus 108, an ISA-PCI bus bridge 110, and a PCI bus 112 to a system controller 114. The system controller 114 then stores the data 116 in the RAM 118 via a memory bus 120. The CPU 106 repeatedly fetches and executes a small number of instructions from the ROM 104 via the ISA bus 108, the ISA-PCI bus bridge 110, the PCI bus 112, the system controller 114, and a CPU bus 122 in order to drive the system controller 114 to transfer the ROM data 102 to the RAM 118. When transfer of the firmware routines is complete, the CPU 106 is then initialized and, following initialization, the CPU fetches and executes the firmware initialization and BIOS routines directly from the system RAM 118 via the memory bus 120, system controller 114, and CPU bus 122. These routines direct the CPU 106 to read the operating system of the PC, or portions thereof, into the RAM 118 from a storage device (not shown), initialize various hardware and software system components (not shown), and thereby bring the PC up to a state where it can be used by a human operator.
Although ROM shadowing vastly increases the speed of PC initialization by speeding up subsequent execution of firmware routines, transfer of the firmware routines to the system RAM 116 in Intel Pentium CPU-based PCs is inefficient. The inefficiencies in ROM shadowing arise largely because the Intel Pentium CPU is not yet initialized when it carries out ROM shadowing. As one result, the instruction cache (not shown) is not available within the CPU 106, requiring the CPU 106 to repeatedly fetch and execute the instructions of a small loop of instructions that transfer the firmware routines from the ROM 104 to the RAM 118. Each instruction is loaded from the ROM 104, via at least one relatively low-speed bus, into a register and then executed in a second step. When a CPU 106 has been initialized, and instruction caching is available, the instructions of a small loop of instructions are fetched only once from the RAM during the first iteration of the loop. The instructions are stored in the CPU instruction cache as they are fetched. When the instructions are needed in a subsequent iteration of the loop, they are fetched from the instruction cache, rather than from the RAM. Instructions in the CPU instruction cache can be fetched more quickly than instructions in memory because, by fetching from the instruction cache, access of instruction through the system controller 114 and either the memory bus 120, in the case of instructions fetched from the RAM 118, or the ISA 108 and PC 112 buses, in the case of instructions fetched from the ROM 104, is avoided. However, in an uninitialized Pentium CPU, caching is not available, and therefore each instruction of the loop of instructions that transfer the firmware routines from the ROM 104 to the RAM 118 must be fetched from the ROM 104 prior to execution during each iteration of the loop.
Intel Pentium processors prefetch instructions. Instruction prefetch allows a CPU to simultaneously execute one instruction while fetching the next instruction from memory. Instruction prefetch is very efficient for executing a linear, sequential series of instructions. It is also efficient when the CPU can correctly predict which of two possible instructions following a branch instruction will be next executed. However, if the instruction being executed causes the processor to branch to an instruction other than the predicted instruction, the instruction being incorrectly prefetched from memory will then need to be discarded from an internal cache within the CPU. CPU execution is stalled until the instruction that is the target of the branch instruction is read from memory by the CPU.
An uninitialized CPU cannot perform effective branch prediction. A second result of carrying out ROM shadowing with an uninitialized CPU is that prefetching will, in a large percentage of cases, obtain the wrong instruction. The loop of instructions used to transfer the firmware routines from the ROM 104 to the RAM 118 is a very tight loop in which a unit of data is transferred from the ROM to the RAM, a counter is decremented, and a branch instruction is executed to return control back to the top of the loop. Thus, a large proportion of the instructions executed during ROM shadowing are branch instructions. Because effective branch prediction cannot be carried out by an uninitialized CPU, the tight loop of instructions used in ROM shadowing effectively defeats the prefetch strategy of the CPU and further slows the ROM shadowing process. A need has therefore been recognized for a way to transfer firmware routines from the ROM to the RAM during PC initialization that does not require execution of a loop of instructions by the CPU.
One embodiment of the present invention in a computer employs hardware circuitry, such as an application-specific integrated circuit (xe2x80x9cASICxe2x80x9d), to transfer ROM data to the system RAM in order to implement ROM shadowing, prior to the initialization of the CPU, as part of the bootstrap process. When this ROM shadowing circuitry detects a system reset signal, the ROM shadowing circuit holds the CPU in a reset state while the ROM shadowing circuit drives the system controller to transfer the ROM data to the RAM. When the ROM data transfer is completed, the ROM shadowing circuit releases the CPU, which then begins fetching and executing instructions from firmware routines included in the ROM data that was transferred to the RAM. The ROM shadowing circuit includes a state machine that incorporates an address counter and a logic circuit that holds the CPU in a reset state while the ROM data is being transferred.